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W305B
Frequency Controller with System Recovery for Intel Integrated Core Logic
Features
* Single chip FTG solution for Intel Solano/810E/810 * Programmable clock output frequency with less than 1 MHz increment * Integrated fail-safe Watchdog timer for system recovery * Automatically switch to HW selected or SW programmed clock frequency when Watchdog timer time-out * Capable of generating system RESET after a Watchdog timer time-out occurs or a change in output frequency via SMBus interface * Support SMBus byte read/write and block read/write operations to simplify system BIOS development * Vendor ID and Revision ID support * Programmable drive strength for SDRAM and PCI output clocks * Programmable output skew between CPU, AGP, PCI and SDRAM * Maximized EMI suppression using Cypress's Spread Spectrum Technology * Low jitter and tightly controlled clock skew * Two copies of CPU clock * Thirteen copies of SDRAM clock * Eight copies of PCI clock * One copy of synchronous APIC clock * Three copies of 66-MHz outputs * Three copies of 48-MHz outputs * One copy of double strength 14.31818-MHz reference clock * One RESET output for system recovery * SMBus interface for turning off unused clocks
Key Specifications
CPU, SDRAM Outputs Cycle-to-Cycle Jitter: ............. 250 ps APIC, 48-MHz, 3V66, PCI Outputs Cycle-to-Cycle Jitter:................................................... 500 ps CPU, 3V66 Output Skew: ........................................... 175 ps SDRAM, APIC, 48-MHz Output Skew: ....................... 250 ps PCI Output Skew: ....................................................... 500 ps CPU to SDRAM Skew (@ 133 MHz) ....................... 0.5 ns CPU to SDRAM Skew (@ 100 MHz) ................. 4.5 to 5.5 ns CPU to 3V66 Skew (@ 66 MHz)........................ 7.0 to 8.0 ns 3V66 to PCI Skew (3V66 lead) .......................... 1.5 to 3.5 ns PCI to APIC Skew..................................................... 0.5 ns
Block Diagram
VDDQ3 REF2X/FS3
PLL REF FREQ
Pin Configuration [1]
GND VDDQ3 REF2X/FS3^ X1 X2 VDDQ3 3V66_0 3V66_1 3V66_2 GND PCI0/FS0^ PCI1/FS1^ PCI2/FS2^ GND PCI3 PCI4 VDDQ3 PCI5 PCI6 PCI7 GND 48MHz 48MHz/FS4^ 24_48MHz/SEL24_48MHz#* VDDQ3 SDATA GND VDDQ3 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 VDDQ2 APIC GND VDDQ2 CPU0 CPU1 GND SDRAM0 SDRAM1 SDRAM2 VDDQ3 GND SDRAM3 SDRAM4 SDRAM5 SDRAM6 VDDQ3 GND SDRAM7 SDRAM8 SDRAM9 SDRAM10 VDDQ3 GND SDRAM11 SDRAM12 RST# SCLK
X1 X2
XTAL OSC
VDDQ2 SDATA SCLK
SMBus Logic
Divider, Delay, and Phase Control Logic
CPU0:1
2
W305B
APIC VDDQ3
3
(FS0:4) 3V66_0:2 PCI0/FS0 PCI1/FS1 PCI2/FS2
5 13
PLL 1
PCI3:7 SDRAM0:12 RST# VDDQ3
48MHz
PLL2
/2
48MHz/FS4 24_48MHz/SEL24_48MHz#
1. Internal 100K pull-up and 100K pull-down resistors present on inputs marked with * and ^ respectively. Design should not rely solely on internal pull-up resistor to set I/O pins HIGH or LOW.
Cypress Semiconductor Corporation Document #: 38-07262 Rev. *B
*
3901 North First Street
*
San Jose, CA 95134 * 408-943-2600 Revised September 1, 2004
W305B
Pin Definitions
Pin Name REF2X/FS3 Pin No. 3 Pin Type I/O Pin Description Reference Clock with 2x Drive/Frequency Select 3. 3.3V 14.318-MHz clock output. This pin also serves as the select strap to determines device operating frequency as described in Table 5. Crystal Input. This pin has dual functions. It can be used as an external 14.318-MHz crystal connection or as an external reference frequency input. Crystal Output. An input connection for an external 14.318-MHz crystal connection. If using an external reference, this pin must be left unconnected. PCI Clock 0/Frequency Selection 0. 3.3V 33-MHz PCI clock outputs. This pin also serves as the select strap to determine device operating frequency as described in Table 5. PCI Clock 1/Frequency Selection 1. 3.3V 33-MHz PCI clock outputs. This pin also serves as the select strap to determine device operating frequency as described in Table 5. PCI Clock 2/Frequency Selection 2. 3.3V 33-MHz PCI clock outputs. This pin also serves as the select strap to determine device operating frequency as described in Table 5. PCI Clock 3 through 7. 3.3V 33-MHz PCI clock outputs. PCI0:7 can be individually turned off via SMBus interface. 66-MHz Clock Output. 3.3V output clocks. The operating frequency is controlled by FS0:4 (see Table 5). 48MHz. 3.3V 48-MHz non-spread spectrum output. 48-MHz Output/Frequency Selection 4. 3.3V 48-MHz non-spread spectrum output. This pin also serves as the select strap to determine device operating frequency as described in Table 5. 24- or 48-MHz Output/Select 24 or 48MHz. 3.3V 24 or 48-MHz non-spread spectrum output. This pin also serves as the select strap to determine the output frequency for 24_48MHz output.
X1 X2 PCI0/FS0
4 5 11
I O I/O
PCI1/FS1
12
I/O
PCI2/FS2
13
I/O
PCI3:7 3V66_0:2 48MHz 48MHz/FS4
15, 16, 18, 19, 20 7, 8, 9 22 23
O O O I/O
24_48MHz/SEL24 _48MHz# RST#
24
I/O
30
O Reset#. Open-drain RESET# output. (open-d rain) O CPU Clock Outputs. Clock outputs for the host bus interface. Output frequencies depending on the configuration of FS0:4. Voltage swing is set by VDDQ2. SDRAM Clock Outputs. 3.3V outputs for SDRAM and chipset. The operating frequency is controlled by FS0:4 (see Table 5). Synchronous APIC Clock Outputs. Clock outputs running synchronous with the PCI clock outputs. Voltage swing set by VDDQ2. Data pin for SMBus circuitry. Clock pin for SMBus circuitry. 3.3V Power Connection. Power supply for SDRAM output buffers, PCI output buffers, reference output buffers and 48-MHz output buffers. Connect to 3.3V. 2.5V Power Connection. Power supply for APIC and CPU output buffers. Connect to 2.5V. Ground Connections. Connect all ground pins to the common system ground plane.
CPU0:1
52, 51
SDRAM0:12,
49, 48, 47, 44, 43, 42, 41, 38, 37, 36, 35, 32, 31 55 26 29 2, 6, 17, 25, 28, 34, 40, 46 53, 56 1, 10, 14, 21, 27, 33, 39, 45, 50, 54
O O I/O I P P G
APIC SDATA SCLK VDDQ3 VDDQ2 GND
Document #: 38-07262 Rev. *B
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W305B
Output Strapping Resistor Series Termination Resistor
W305B Power-on Reset Timer Output Buffer Output Three-state
Q
Clock Load
Hold Output Low
D
10 k
Data Latch
Figure 1. Input Logic Selection Through Resistor Load Option
Overview
The W305B is a highly integrated frequency timing generator, supplying all the required clock sources for an Intel(R) architecture platform using graphics integrated core logic.
Functional Description
I/O Pin Operation Upon power-up the power on strap option pins act as a logic input. An external 10-k strapping resistor should be used. Figure 1 shows a suggested method for strapping resistor connections.
0 ns 10 ns 20 ns
After 2 ms, the pin becomes an output. Assuming the power supply has stabilized by then, the specified output frequency is delivered on the pins. If the power supply has not yet reached full value, output frequency initially may be below target but will increase to target once supply voltage has stabilized. In either case, a short output clock cycle may be produced from the CPU clock outputs when the outputs are enabled. Offsets Among Clock Signal Groups Figure 2, Figure 3, and Figure 4 represent the phase relationship among the different groups of clock outputs from W305B under different frequency modes.
30 ns 40 ns
CPU 66-MHz
CPU 66 Period
SDRAM 100-MHz
SDRAM 100 Period
3V66 66-MHz PCI 33-MHz REF 14.318-MHz USB 48-MHz APIC 16.6-MHz
Hub-PCI
Figure 2. Group Offset Waveforms (66-MHz CPU Clock, 100-MHz SDRAM Clock)
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W305B
0 ns 10 ns 20 ns 30 ns 40 ns
CPU 100-MHz
CPU 100 Period
SDRAM 100 Period
SDRAM 100-MHz
3V66 66-MHz
PCI 33-MHz REF 14.318-MHz USB 48-MHz APIC16.6-MHz
Hub-PC
Figure 3. Group Offset Waveforms (100-MHz CPU Clock, 100-MHz SDRAM Clock)
0 ns
10 ns
20 ns
30 ns
40 ns
CPU 133-MHz
Cycle Repeats
SDRAM 100-MHz 3V66 66-MHz PCI 33-MHz APIC 16.6-MHz REF 14.318-MHz USB 48-MHz DOT 48-MHz
Figure 4. Group Offset Waveforms (133-MHz CPU/100-MHz SDRAM)
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W305B
0 ns 10 ns 20 ns 30 ns 40 ns
CPU 133-MHz
Cycle Repeat
SDRAM 133MHz 3V66 66-MHz PCI 33-MHz APIC 16.6-MHz REF 14.318-MHz USB 48-MHz DOT 48-MHz
Figure 5. Group Offset Waveform (133-MHz CPU/133-MHz SDRAM) Serial Data Interface The W305B features a two-pin, serial data interface that can be used to configure internal register settings that control particular device functions. Data Protocol The clock driver serial protocol supports byte/word write, byte/word read, block write and block read operations from the Table 1. Command Code Definition Bit 7 6:0 Descriptions 0 = Block read or block write operation 1 = Byte/Word read or byte/word write operation Byte offset for byte/word read or write operation. For block read or write operations, these bits need to be set at `0000000'. controller. For block write/read operation, the bytes must be accessed in sequential order from lowest to highest byte with the ability to stop after any complete byte has been transferred. For byte/word write and byte read operations, system controller can access individual indexed byte. The offset of the indexed byte is encoded in the command code. The definition for the command code is given in Table 1.
Table 2. Block Read and Block Write Protocol Block Write Protocol Bit 1 2:8 9 10 11:18 19 20:27 28 29:36 37 38:45 46 ... Start Slave address - 7 bit Write Acknowledge from slave Command Code - 8 bit `00000000' stands for block operation Acknowledge from slave Byte Count - 8 bits Acknowledge from slave Data byte 0 - 8 bits Acknowledge from slave Data byte 1 - 8 bits Acknowledge from slave Data Byte N/Slave Acknowledge... Description Bit 1 2:8 9 10 11:18 19 20 21:27 28 29 30:37 38 39:46 Start Slave address - 7 bit Write Acknowledge from slave Command Code - 8 bit `00000000' stands for block operation Acknowledge from slave Repeat start Slave address - 7 bits Read Acknowledge from slave Byte count from slave - 8 bits Acknowledge Data byte from slave - 8 bits Page 5 of 21 Block Read Protocol Description
Document #: 38-07262 Rev. *B
W305B
Table 2. Block Read and Block Write Protocol (continued) Block Write Protocol Bit ... ... ... Description Data Byte N - 8 bits Acknowledge from slave Stop Bit 47 48:55 56 ... ... ... ... Table 3. Word Read and Word Write Protocol Word Write Protocol Bit 1 2:8 9 10 11:18 Start Slave address - 7 bit Write Acknowledge from slave Command Code - 8 bit `1xxxxxxx' stands for byte or word operation bit[6:0] of the command code represents the offset of the byte to be accessed Acknowledge from slave Data byte low- 8 bits Acknowledge from slave Data byte high - 8 bits Acknowledge from slave Stop Description Bit 1 2:8 9 10 11:18 Start Slave address - 7 bit Write Acknowledge from slave Command Code - 8 bit `1xxxxxxx' stands for byte or word operation bit[6:0] of the command code represents the offset of the byte to be accessed Acknowledge from slave Repeat start Slave address - 7 bits Read Acknowledge from slave Data byte low from slave - 8 bits Acknowledge Data byte high from slave - 8 bits NOT acknowledge Stop Word Read Protocol Description Acknowledge Data byte from slave - 8 bits Acknowledge Data bytes from slave/Acknowledge Data byte N from slave - 8 bits Not Acknowledge Stop Block Read Protocol Description
19 20:27 28 29:36 37 38
19 20 21:27 28 29 30:37 38 39:46 47 48
Table 4. Byte Read and Byte Write Protocol Byte Write Protocol Bit 1 2:8 9 10 11:18 Start Slave address - 7 bit Write Acknowledge from slave Command Code - 8 bit `1xxxxxxx' stands for byte operation bit[6:0] of the command code represents the offset of the byte to be accessed Acknowledge from slave Data byte - 8 bits Acknowledge from slave Stop Description Bit 1 2:8 9 10 11:18 Start Slave address - 7 bit Write Acknowledge from slave Command Code - 8 bit `1xxxxxxx' stands for byte operation bit[6:0] of the command code represents the offset of the byte to be accessed Acknowledge from slave Repeat start Slave address - 7 bits Read Page 6 of 21 Byte Read Protocol Description
19 20:27 28 29
19 20 21:27 28
Document #: 38-07262 Rev. *B
W305B
Table 4. Byte Read and Byte Write Protocol (continued) Byte Write Protocol Bit Description Bit 29 30:37 38 39 W305B Serial Configuration Map The serial bits will be read by the clock driver in the following order: Byte 0 - Bits 7, 6, 5, 4, 3, 2, 1, 0 Byte 1 - Bits 7, 6, 5, 4, 3, 2, 1, 0 Byte 0: Control Register 0 Bit Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Pin# SEL4 SEL3 SEL2 SEL1 SEL0 Spread Select2 Spread Select1 Spread Select0 Name Default 0 0 0 0 0 0 0 0 See Table 5 See Table 5 See Table 5 See Table 5 See Table 5 `000' = Normal (spread off) `001' = Test Mode `010' = Reserved `011' = Three-Stated `100' = -0.5% `101' = 0.5% `110' = 0.25% `111' = 0.38% Byte 1: Control Register 1 Bit Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Byte 2: Control Register 2 Bit Bit 7 Bit 6 Bit 5 Bit 4 Pin# 20 19 18 16 PCI7 PCI6 PCI5 PCI4 Name Default 1 1 1 1 (Active/Inactive) (Active/Inactive) (Active/Inactive) (Active/Inactive) Page 7 of 21 Description Pin# 23 3 13 12 11 3 Name Latched FS4 input Latched FS3 input Latched FS2 input Latched FS1 input Latched FS0 input Reserved REF2X Reserved Default X X X X X 0 1 0 Reserved (Active/Inactive) Reserved Description Latched FS[4:0] inputs. These bits are read only. Description Byte Read Protocol Description Acknowledge from slave Data byte from slave - 8 bits Not Acknowledge Stop
Byte N - Bits 7, 6, 5, 4, 3, 2, 1, 0 All unused register bits (reserved and N/A) should be written to a "0" level. All register bits labeled "Initialize to 0" must be written to zero during initialization.
Document #: 38-07262 Rev. *B
W305B
Byte 2: Control Register 2 (continued) Bit Bit 3 Bit 2 Bit 1 Bit 0 Byte 3: Control Register 3 Bit Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Byte 4: Control Register 4 Bit Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Byte 5: Control Register 5 Bit Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Pin# 31 32 35 36 37 Name Reserved Reserved Reserved SDRAM12 SDRAM11 SDRAM10 SDRAM9 SDRAM8 Default 0 0 0 1 1 1 1 1 Reserved Reserved Reserved (Active/Inactive) (Active/Inactive) (Active/Inactive) (Active/Inactive) (Active/Inactive) Description Pin# 38 41 42 43 44 47 48 49 Name SDRAM7 SDRAM6 SDRAM5 SDRAM4 SDRAM3 SDRAM2 SDRAM1 SDRAM0 Default 1 1 1 1 1 1 1 1 (Active/Inactive) (Active/Inactive) (Active/Inactive) (Active/Inactive) (Active/Inactive) (Active/Inactive) (Active/Inactive) (Active/Inactive) Description Pin# 9 8 7 55 51 52 Name 3V66_2 3V66_1 3V66_0 APIC Reserved Reserved CPU1 CPU0 Default 1 1 1 1 0 0 1 1 (Active/Inactive) (Active/Inactive) (Active/Inactive) (Active/Inactive) Reserved Reserved (Active/Inactive) (Active/Inactive) Description Pin# 15 13 12 11 PCI3 PCI2 PCI1 PCI0 Name Default 1 1 1 1 (Active/Inactive) (Active/Inactive) (Active/Inactive) (Active/Inactive) Description
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W305B
Byte 6: Vendor ID & Revision ID Register (Read Only) Bit Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Name Revision_ID3 Revision_ID2 Revision_ID1 Revision_ID0 Vendor_ID3 Vendor_ID2 Vendor _ID1 Vendor _ID0 Default 0 0 0 0 1 0 0 0 Revision ID bit[3] Revision ID bit[2] Revision ID bit[1] Revision ID bit[0] Bit[3] of Cypress Semiconductor's Vendor ID. This bit is read only. Bit[2] of Cypress Semiconductor's Vendor ID. This bit is read only. Bit[1] of Cypress Semiconductor's Vendor ID. This bit is read only. Bit[0] of Cypress Semiconductor's Vendor ID. This bit is read only. Pin Description
Byte 7: Control Register 7 Bit Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Pin# 24 23 22 24 23 22 -Name Reserved 24_48MHz_DRV 48MHz_DRV 48MHz_DRV 24_48MHz 48 MHz 48 MHz Reserved Default 0 1 1 1 1 1 1 0 Reserved 0 = Norm, 1 = High Drive 0 = Norm, 1 = High Drive 0 = Norm, 1 = High Drive (Active/Inactive) (Active/Inactive) (Active/Inactive) Reserved Pin Description
Byte 8: Watchdog Timer Register Bit Bit 7 Bit 6 Name PCI_Skew1 PCI_Skew0 Default 0 0 PCI skew control 00 = Normal 01 = -500ps 10 = Reserved 11 = +500ps These bits store the time-out value of the Watchdog timer. The scale of the timer is determine by the pre-scaler. The timer can support a value of 150 ms to 4.8 sec when the pre-scaler is set to 150 ms. If the pre-scaler is set to 2.5 sec, it can support a value from 2.5 sec. to 80 sec. When the Watchdog timer reaches "0", it will set the WD_TO_STATUS bit. 0 = 150 ms 1 = 2.5 sec Pin Description
Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
WD_TIMER4 WD_TIMER3 WD_TIMER2 WD_TIMER1 WD_TIMER0 WD_PRE_SCALER
1 1 1 1 1 0
Byte 9: System RESET and Watchdog Timer Register Bit Bit 7 Name SDRAM_DRV Default 0 Pin Description SDRAM clock output drive strength 0 = Normal 1 = High Drive PCI clock output drive strength 0 = Normal 1 = High Drive 0 = Select operating frequency by FS[4:0] input pins 1 = Select operating frequency by SEL[4:0] settings
Bit 6
PCI_DRV
0
Bit 5
FS_Override
0
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W305B
Byte 9: System RESET and Watchdog Timer Register (continued) Bit Bit 4 Name RST_EN_WD Default 0 Pin Description This bit will enable the generation of a Reset pulse when a watchdog timer time-out occurs. 0 = Disabled 1 = Enabled This bit will enable the generation of a Reset pulse after a frequency change occurs. 0 = Disabled 1 = Enabled Watchdog Timer Time-out Status bit 0 = No time-out occurs (READ); Ignore (WRITE) 1 = time-out occurred (READ); Clear WD_TO_STATUS (WRITE) 0 = Stop and re-load Watchdog timer. Unlock W305B from recovery frequency mode. 1 = Enable Watchdog timer. It will start counting down after a frequency change occurs. Note: W305B will generate system reset, re-load a recovery frequency, and lock itself into a recovery frequency mode after a Watchdog timer time-out occurs. Under recovery frequency mode, W305B will not respond to any attempt to change output frequency via the SMBus control bytes. System software can unlock W305B from its recovery frequency mode by clearing the WD_EN bit. Reserved
Bit 3
RST_EN_FC
0
Bit 2
WD_TO_STATUS
0
Bit 1
WD_EN
0
Bit 0
Reserved
0
Byte 10: Skew Control Register Bit Bit 7 Bit 6 Bit 5 Name CPU_Skew2 CPU_Skew1 CPU_Skew0 Default 0 0 0 CPU skew control 000 = Normal 001 = -150 ps 010 = -300 ps 011 = -450 ps 100 = +150 ps 101 = +300 ps 110 = +450 ps 111 = +600 ps SDRAM skew control 000 = Normal 001 = -150 ps 010 = -300 ps 011 = -450 ps 100 = +150 ps 101 = +300 ps 110 = +450 ps 111 = +600 ps AGP skew control 00 = Normal 01 = -150ps 10 = +150ps 11 = +300ps Description
Bit 4 Bit 3 Bit 2
SDRAM_Skew2 SDRAM_Skew1 SDRAM_Skew0
0 0 0
Bit 1 Bit 0
AGP_Skew1 AGP_Skew0
0 0
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W305B
Byte 11: Recovery Frequency N-Value Register Bit Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Name ROCV_FREQ_N7 ROCV_FREQ_N6 ROCV_FREQ_N5 ROCV_FREQ_N4 ROCV_FREQ_N3 ROCV_FREQ_N2 ROCV_FREQ_N1 ROCV_FREQ_N0 Default 0 0 0 0 0 0 0 0 Pin Description If ROCV_FREQ_SEL is set, W305B will use the values programmed in ROCV_FREQ_N[7:0] and ROCV_FREQ_M[6:0] to determine the recovery CPU output frequency.when a Watchdog timer time-out occurs The setting of FS_Override bit determines the frequency ratio for CPU, SDRAM, AGP and SDRAM. When it is cleared, W305B will use the same frequency ratio stated in the Latched FS[4:0] register. When it is set, W305B will use the frequency ratio stated in the SEL[4:0] register. W305B supports programmable CPU frequency ranging from 50 MHz to 248 MHz. W305Bwill change the output frequency whenever there is an update to either ROCV_FREQ_N[7:0] and ROCV_FREQ_M[6:0]. Therefore, it is recommended to use Word or Block write to update both registers within the same SMBus bus operation.
Byte 12: Recovery Frequency M-Value Register Bit Bit 7 Name ROCV_FREQ_SEL Default 0 Pin Description ROCV_FREQ_SEL determines the source of the recover frequency when a Watchdog timer time-out occurs. The clock generator will automatically switch to the recovery CPU frequency based on the selection on ROCV_FREQ_SEL. 0 = From latched FS[4:0] 1 = From the settings of ROCV_FREQ_N[7:0] & ROCV_FREQ_M[6:0] If ROCV_FREQ_SEL is set, W305B will use the values programmed in ROCV_FREQ_N[7:0] and ROCV_FREQ_M[6:0] to determine the recovery CPU output frequency.when a Watchdog timer time-out occurs The setting of FS_Override bit determines the frequency ratio for CPU, SDRAM, AGP and SDRAM. When it is cleared, W305B will use the same frequency ratio stated in the Latched FS[4:0] register. When it is set, W305B will use the frequency ratio stated in the SEL[4:0] register. W305B supports programmable CPU frequency ranging from 50 MHz to 248 MHz. W305B will change the output frequency whenever there is an update to either ROCV_FREQ_N[7:0] and ROCV_FREQ_M[6:0]. Therefore, it is recommended to use Word or Block write to update both registers within the same SMBus bus operation.
Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
ROCV_FREQ_M6 ROCV_FREQ_M5 ROCV_FREQ_M4 ROCV_FREQ_M3 ROCV_FREQ_M2 ROCV_FREQ_M1 ROCV_FREQ_M0
0 0 0 0 0 0 0
Byte 13: Programmable Frequency Select N-Value Register Bit Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Name CPU_FSEL_N7 CPU_FSEL_N6 CPU_FSEL_N5 CPU_FSEL_N4 CPU_FSEL_N3 CPU_FSEL_N2 CPU_FSEL_N1 CPU_FSEL_N0 Default 0 0 0 0 0 0 0 0 Pin Description If Prog_Freq_EN is set, W305B will use the values programmed in CPU_FSEL_N[7:0] and CPU_FSEL_M[6:0] to determine the CPU output frequency. The new frequency will start to load whenever CPU_FSELM[6:0] is updated. The setting of FS_Override bit determines the frequency ratio for CPU, SDRAM, AGP and SDRAM. When it is cleared, W305B will use the same frequency ratio stated in the Latched FS[4:0] register. When it is set, W305B will use the frequency ratio stated in the SEL[4:0] register. W305B supports programmable CPU frequency ranging from 50 MHz to 248 MHz.
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W305B
Byte 14: Programmable Frequency Select M-Value Register Bit Bit 7 Name Pro_Freq_EN Default 0 Description Programmable output frequencies enabled 0 = disabled 1 = enabled If Prog_Freq_EN is set, W305B will use the values programmed in CPU_FSEL_N[7:0] and CPU_FSEL_M[6:0] to determine the CPU output frequency. The new frequency will start to load whenever CPU_FSELM[6:0] is updated. The setting of FS_Override bit determines the frequency ratio for CPU, SDRAM, AGP and SDRAM. When it is cleared, W305B will use the same frequency ratio stated in the Latched FS[4:0] register. When it is set, W305B will use the frequency ratio stated in the SEL[4:0] register. W305B supports programmable CPU frequency ranging from 50 MHz to 248 MHz.
Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
CPU_FSEL_M6 CPU_FSEL_M5 CPU_FSEL_M4 CPU_FSEL_M3 CPU_FSEL_M2 CPU_FSEL_M1 CPU_FSEL_M0
0 0 0 0 0 0 0
Byte 15: Reserved Register Bit Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Byte 16: Reserved Register Bit Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Byte 17: Reserved Register Bit Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Pin# Name Reserved Reserved Reserved Reserved Reserved Reserved Reserved Default 0 0 0 0 0 0 0 Reserved Reserved Reserved Reserved Reserved Reserved Reserved Description Pin# Name Reserved Reserved Reserved Reserved Reserved Reserved Reserved Default 0 0 0 0 0 0 0 Reserved Reserved Reserved Reserved Reserved Reserved Reserved Description Pin# Name Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Default 0 0 0 0 0 0 1 1 Reserved Reserved Reserved Reserved Reserved Reserved Reserved. Write with `1' Reserved. Write with `1' Description
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W305B
Table 5. Additional Frequency Selections through Serial Data Interface Data Bytes Input Conditions FS4 SEL4 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 FS3 SEL3 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 FS2 SEL2 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 FS1 SEL1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 FS0 SEL0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 CPU 66.6 120.0 66.8 68.3 70.0 75.0 80.0 83.0 100.0 124.0 100.2 103.0 105.0 110.0 115.0 200.0 133.3 166.6 133.6 137.0 140.0 145.0 150.0 160.0 133.3 166.6 133.6 137.0 66.6 100.0 133.3 133.3 SDRAM 100.0 120.0 100.2 102.5 105.0 112.5 120.0 124.5 100.0 124.0 100.2 103.0 105.0 110.0 115.0 200.0 133.3 166.6 133.6 137.0 140.0 145.0 150.0 160.0 100.0 125.0 100.2 102.8 100.0 100.0 133.3 100.0 3V66 66.6 80.0 66.8 68.3 70.0 75.0 80.0 83.0 66.6 82.6 66.8 68.9 70.0 73.3 76.6 66.6 66.6 83.3 66.8 68.5 70.0 72.5 75.0 80.0 66.6 83.3 66.8 68.5 66.6 66.6 66.6 66.6 PCI 33.3 40.0 33.4 34.2 35.0 37.5 40.0 41.5 33.3 41.3 33.4 34.3 35.0 36.7 38.3 33.3 33.3 41.6 33.4 34.3 35.0 36.2 37.5 40.0 33.3 41.7 33.4 34.3 33.3 33.3 33.3 33.3 APIC 16.6 20.0 16.7 17.1 17.5 18.8 20.0 20.8 16.6 20.6 16.7 17.2 17.5 18.3 19.1 16.6 16.6 20.8 16.7 17.1 17.5 18.1 18.7 20.0 16.6 20.8 16.7 17.1 16.6 16.6 16.6 16.6 Output Frequency PLL Gear Constants (G) 32.00494 48.00741 32.00494 32.00494 32.00494 32.00494 32.00494 32.00494 48.00741 48.00741 48.00741 48.00741 48.00741 48.00741 48.00741 96.01482 64.00988 64.00988 64.00988 64.00988 64.00988 64.00988 64.00988 64.00988 64.00988 64.00988 64.00988 64.00988 32.00494 48.00741 64.00988 64.00988
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W305B
Programmable Output Frequency, Watchdog Timer and Recovery Output Frequency Functional Description
The Programmable Output Frequency feature allows users to generate any CPU output frequency from the range of 50 MHz to 248 MHz. Cypress offers the most dynamic and the simplest programming interface for system developers to utilize this feature in their platforms. Table 6. Register Summary Name Pro_Freq_EN Programmable output frequencies enabled 0 = disabled (default) 1 = enabled When it is disabled, the operating output frequency will be determined by either the latched value of FS[4:0] inputs or the programmed value of SEL[4:0]. If FS_Override bit is clear, latched FS[4:0] inputs will be used. If FS_Override bit is set, programmed value of SEL[4:0] will be used. When it is enabled, the CPU output frequency will be determined by the programmed value of CPUFSEL_N, CPUFSEL_M and the PLL Gear Constant. The program value of FS_Override, SEL[4:0] or the latched value of FS[4:0] will determine the PLL Gear Constant and the frequency ratio between CPU and other frequency outputs FS_Override When Pro_Freq_EN is cleared or disabled, 0 = Select operating frequency by FS input pins (default) 1 = Select operating frequency by SEL bits in SMBus control bytes When Pro_Freq_EN is set or enabled, 0 = Frequency output ratio between CPU and other frequency groups and the PLL Gear Constant are based on the latched value of FS input pins (default) 1 = Frequency output ratio between CPU and other frequency groups and the PLL Gear Constant are based on the programmed value of SEL bits in SMBus control bytes CPU_FSEL_N, CPU_FSEL_M When Prog_Freq_EN is set or enabled, the values programmed in CPU_FSEL_N[7:0] and CPU_FSEL_M[6:0] determines the CPU output frequency. The new frequency will start to load whenever there is an update to either CPU_FSEL_N[7:0] or CPU_FSEL_M[6:0]. Therefore, it is recommended to use Word or Block write to update both registers within the same SMBus bus operation. The setting of FS_Override bit determines the frequency ratio for CPU, SDRAM, AGP and SDRAM. When FS_Override is cleared or disabled, the frequency ratio follows the latched value of the FS input pins. When FS_Override is set or enabled, the frequency ratio follows the programmed value of SEL bits in SMBus control bytes. ROCV_FREQ_SEL ROCV_FREQ_SEL determines the source of the recover frequency when a Watchdog timer time-out occurs. The clock generator will automatically switch to the recovery CPU frequency based on the selection on ROCV_FREQ_SEL. 0 = From latched FS[4:0] 1 = From the settings of ROCV_FREQ_N[7:0] & ROCV_FREQ_M[6:0] When ROCV_FREQ_SEL is set, the values programmed in ROCV_FREQ_N[7:0] and ROCV_FREQ_M[6:0] will be used to determine the recovery CPU output frequency when a Watchdog timer time-out occurs The setting of FS_Override bit determines the frequency ratio for CPU, SDRAM, AGP and SDRAM. When it is cleared, the same frequency ratio stated in the Latched FS[4:0] register will be used. When it is set, the frequency ratio stated in the SEL[4:0] register will be used. The new frequency will start to load whenever there is an update to either ROCV_FREQ_N[7:0] and ROCV_FREQ_M[6:0]. Therefore, it is recommended to use Word or Block write to update both registers within the same SMBus bus operation. Description The Watchdog Timer and Recovery Output Frequency features allow users to implement a recovery mechanism when the system hangs or getting unstable. System BIOS or other control software can enable the Watchdog timer before they attempt to make a frequency change. If the system hangs and a Watchdog timer time-out occurs, a system reset will be generated and a recovery frequency will be activated. All the related registers are summarized in the following table.
ROCV_FREQ_N[7:0], ROCV_FREQ_M[6:0]
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W305B
Table 6. Register Summary (continued) Name WD_EN Description 0 = Stop and re-load Watchdog timer. Unlock W305B from recovery frequency mode. 1 = Enable Watchdog timer. It will start counting down after a frequency change occurs. Note. W305B will generate system reset, re-load a recovery frequency, and lock itself into a recovery frequency mode after a Watchdog timer time-out occurs. Under recovery frequency mode, W305B will not respond to any attempt to change output frequency via the SMBus control bytes. System software can unlock W305B from its recovery frequency mode by clearing the WD_EN bit. Watchdog Timer Time-out Status bit 0 = No time-out occurs (READ); Ignore (WRITE) 1 = time-out occurred (READ); Clear WD_TO_STATUS (WRITE) These bits store the time-out value of the Watchdog timer. The scale of the timer is determine by the pre-scaler. The timer can support a value of 150 ms to 4.8 sec. when the pre-scaler is set to 150 ms. If the pre-scaler is set to 2.5 sec, it can support a value from 2.5 sec to 80 sec. When the Watchdog timer reaches "0", it will set the WD_TO_STATUS bit. 0 = 150 ms 1 = 2.5 sec This bit will enable the generation of a Reset pulse when a watchdog timer time-out occurs. 0 = Disabled 1 = Enabled This bit will enable the generation of a Reset pulse after a frequency change occurs. 0 = Disabled 1 = Enabled "G" stands for the PLL Gear Constant, which is determined by the programmed value of FS[4:0] or SEL[4:0]. The value is listed in Table 5. The following table lists the recommended frequency output ranges for each PLL Gear Constant and its associated Bus Frequency Ratio so that the maximum AGP and PCI output frequencies are less than or equal to 83.1 MHz and 41.5 MHz, respectively.
WD_TO_STATUS
WD_TIMER[4:0]
WD_PRE_SCALER RST_EN_WD
RST_EN_FC
How to Program CPU Output Frequency When the programmable output frequency feature is enabled (Pro_Freq_EN bit is set), the CPU output frequency is determined by the following equation: Fcpu = G * (N+3)/(M+3) "N" and "M" are the values programmed in Programmable Frequency Select N-Value Register and M-Value Register, respectively.
Table 7. Recommended CPU Frequency Range for Different PLL Gear Ratio Recommended Output Frequency Range (CPU/SDRAM/AGP/PCI) Gear Constants G1 (32.00494) G2 (48.00741) G3 (64.00988) Bus Frequency Ratio (CPU/SDRAM/AGP/PCI) 66 / 100 / 66 / 33 100 / 100 / 66 / 33 133 / 133 / 66 / 33 or 133 / 100 / 66 / 33 200 / 200 / 66 / 33 Lower Limits (N=77, M=48) 50.2 / 75.8 / 50.2 / 25.1 75.3 / 75.3 / 50.2 / 25.1 100.4 / 100.4 / 50.2 / 25.1 or 100.4 / 75.3 / 50.2 / 25.1 150.6 / 150.6 / 50.2 / 25.1 Upper Limits (N=106, M=39) 83.1 / 124.7 / 83.1 / 41.5 124.6 / 124.6 / 83.1 / 41.5 166.1 / 166.1 / 83.1 / 41.5 or 166.1 / 124.5 / 83.1 / 41.5 249.2 / 249.2 / 83.1 / 41.5
G4 (96.01482)
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W305B
Absolute Maximum DC Power Supply
Parameter VDDQ3 VDDQ2 TS Description 3.3V Core Supply Voltage 2.5V I/O Supply Voltage Storage Temperature Min. -0.5 -0.5 -65 Max. 4.6 3.6 150 Unit V V C
Absolute Maximum DC I/O
Parameter Vi/o3 Vi/o3 ESD prot. Description 3.3V Core Supply Voltage 2.5V I/O Supply Voltage Input ESD Protection Min. -0.5 -0.5 2000 Max. 4.6 3.6 Unit V V V
DC Electrical Characteristics [2]
DC parameters must be sustainable under steady state (DC) conditions. DC Operating Requirements Parameter VDD3 VDDQ3 VDDQ2 VDD3 = 3.3V5% Vih3 Vil3 Iil VDDQ2 = 2.5V5% Voh2 Vol2 VDDQ3 = 3.3V5% Voh3 Vol3 VDDQ3 = 3.3V5% Vpoh3 Vpol3 Cin Cxtal Cout Lpin Ta PCI Bus Output High Voltage PCI Bus Output Low Voltage Input Pin Capacitance Xtal Pin Capacitance Output Pin Capacitance Pin Inductance Ambient Temperature No Airflow 0 0 13.5 Ioh=(-1 mA) Iol=(1 mA) 2.4 0.55 5 22.5 6 7 70 V V pF pF pF nH C 3.3V Output High Voltage 3.3V Output Low Voltage Ioh=(-1 mA) Iol=(1 mA) 2.4 0.4 V V 2.5V Output High Voltage 2.5V Output Low Voltage Ioh=(-1 mA) Iol=(1 mA) 2.0 0.4 V V 3.3V Input High Voltage 3.3V Input Low Voltage Input Leakage Current[3] 0Notes: 2. Multiple Supplies: The voltage on any input or I/O pin cannot exceed the power pin during power-up. Power supply sequencing is NOT req 3. Input Leakage Current does not include inputs with pull-up or pull-down resistors.
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W305B
AC Electrical Characteristics TA = 0C to +70C, VDDQ3 = 3.3V5%, VDDQ2= 2.5V5%fXTL = 14.31818 MHz[2]
66.6-MHz Host Parameter TPeriod THIGH TLOW TRISE TFALL TPeriod THIGH TLOW TRISE TFALL TPeriod THIGH TLOW TRISE TFALL TPeriod THIGH TLOW TRISE TFALL TPeriod THIGH TLOW TRISE TFALL tpZL, tpZH tpLZ, tpZH tstable Description Host/CPUCLK Period Host/CPUCLK High Time Host/CPUCLK Low Time Host/CPUCLK Rise Time Host/CPUCLK Fall Time SDRAM CLK Period SDRAM CLK High Time SDRAM CLK Low Time SDRAM CLK Rise Time SDRAM CLK Fall Time APIC CLK Period APIC CLK High Time APIC CLK Low Time APIC CLK Rise Time APIC CLK Fall Time 3V66 CLK Period 3V66 CLK High Time 3V66 CLK Low Time 3V66 CLK Rise Time 3V66 CLK Fall Time PCI CLK Period PCI CLK High Time PCI CLK Low Time PCI CLK Rise Time PCI CLK Fall Time Output Enable Delay (All outputs) Output Disable Delay (All outputs) All Clock Stabilization from Power-Up Min. 15.0 5.2 5.0 0.4 0.4 10.0 3.0 2.8 0.4 0.4 60.0 25.5 25.3 0.4 0.4 15.0 5.25 5.05 0.5 0.5 30.0 12.0 12.0 0.5 0.5 1.0 1.0 Max. 15.5 N/A N/A 1.6 1.6 10.5 N/A N/A 1.6 1.6 64.0 N/A N/A 1.6 1.6 16.0 N/A N/A 2.0 2.0 N/A N/A N/A 2.0 2.0 10.0 10.0 3 100-MHz Host Min. 10.0 3.0 2.8 0.4 0.4 10.0 3.0 2.8 0.4 0.4 60.0 25.5 25.30 0.4 0.4 15.0 5.25 5.05 0.5 0.5 30.0 12.0 12.0 0.5 0.5 1.0 1.0 Max. 10.5 N/A N/A 1.6 1.6 10.5 N/A N/A 1.6 1.6 N/A N/A N/A 1.6 1.6 16.0 N/A N/A 2.0 2.0 N/A N/A N/A 2.0 2.0 10.0 10.0 3 133-MHz Host Min. 7.5 1.87 1.67 0.4 0.4 10.0 3.0 2.8 0.4 0.4 60.0 25.5 25.30 0.4 0.4 15.0 5.25 5.05 0.5 0.5 30.0 12.0 12.0 0.5 0.5 1.0 1.0 Max. 8.0 N/A N/A 1.6 1.6 10.5 N/A N/A 1.6 1.6 64.0 N/A N/A 1.6 1.6 16.0 N/A N/A 2.0 2.0 N/A N/A N/A 2.0 2.0 10.0 10.0 3 Unit ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ms 4, 7 4 5 4, 5 4 5 4 4 5 4 4 5 4 4,7 5 Notes
Notes: 4. Period, jitter, offset, and skew measured on rising edge at 1.25 for 2.5V clocks and at 1.5V for 3.3V clocks. 5. The time specified is measured from when VDDQ3 achieves its nominal operating level (typical condition VDDQ3 = 3.3V) until the frequency output is stable and operating within specification. 6. TRISE and TFALL are measured as a transition through the threshold region Vol = 0.4V and Voh = 2.0V (1 mA) JEDEC specification. 7. TLOW is measured at 0.4V for all outputs. 8. THIGH is measured at 2.0V for 2.5V outputs, 2.4V for 3.3V outputs.
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W305B
Group Skew and Jitter Limits Output Group CPU SDRAM APIC 48MHz 3V66 PCI REF Pin-Pin Skew Max. 175 ps 250 ps 250 ps 250 ps 175 ps 500 ps N/A Cycle-Cycle Jitter 250 ps 250 ps 500 ps 500 ps 500 ps 500 ps 1000 ps Duty Cycle 45/55 45/55 45/55 45/55 45/55 45/55 45/55 Nom Vdd 2.5V 3.3V 2.5V 3.3V 3.3V 3.3V 3.3V Skew, Jitter Measure Point 1.25V 1.5V 1.25V 1.5V 1.5V 1.5V 1.5V
Output Buffer Clock Output Wave
Test Point
Test Load TPERIOD Duty Cycle THIGH
2.0
2.5V Clocking Interface
1.25 0.4
TLOW TRISE TFALL TPERIOD Duty Cycle THIGH
2.4
3.3V Clocking Interface
1.5 0.4
TLOW TRISE TFALL
Figure 6. Output Buffer
Ordering Information
Ordering Code W305BH W305BHH Lead Free CYW305OXC CYW305OXCT 56-pin SSOP (300 mils) 56-pin SSOP (300 mils) - Tape and Reel Commercial Commercial Package Type 56-pin SSOP (300 mils) 56-pin SSOP (300 mils) - Tape and Reel Operating Range Commercial Commercial
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W305B
Layout Example
+3.3V Supply FB
VDDQ3 VDDQ2
+2.5V Supply FB
10 mF
C4
.005 mF
C3
C1 G V G V G V G
10 mF
.005 mf
C2
G
G
G
G G
G
G
1 2 3 4 5 6 7 8 9
10
V G
G V
G
G
+3.3V
5
C5 G 10 F
G C6 0.1 F G
11 12 13 14 G 15 16 G 17 V 18 G 19 20 21 G 22 23 24 25 26 27 G 28 V
G
G V G
G V G
G
56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29
G
G
G
FB = Dale ILB1206 - 300 (300 @ 100 MHz) or TDK ACB 2012L-120 Cermaic Cap C1, C3 & C5 = 10 - 22 F G = VIA to GND plane layer C2 & C4 = .005 F C6 = 0.1 F
Note: Each supply plane or strip should have a ferrite bead and capacitors
W305B
G
G
V =VIA to respective supply plane layer
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W305B
Package Drawing Dimension
56-Lead Shrunk Small Outline Package O56
.020
28 1
0.395 0.420 0.292 0.299
DIMENSIONS IN INCHES MIN.
MAX.
29
56
0.720 0.730 SEATING PLANE 0.088 0.092 0.095 0.110
GAUGE PLANE
.010
0.005 0.010
0.025 BSC
0.110 0.008 0.0135 0.008 0.016 0-8
0.024 0.040
51-85062-*C
All product and company names mentioned in this document are trademarks of their respective holders.
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(c) Cypress Semiconductor Corporation, 2004. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges.
W305B
Document History Page
Document Title: W305B Frequency Controller with System Recovery for Intel Integrated Core Logic Document Number: 38-07262 REV. ** *A *B ECN NO. 110527 122861 260010 Issue Date 12/02/01 12/22/02 See ECN Orig. of Change SZV RBI RGL Description of Change Change from Spec number: 38-01099 to 38-07262 Added power up requirements to Recommended Operating Conditions Added Lead Free Devices
Document #: 38-07262 Rev. *B
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